Client Side Verilog Synthesis

This project migrates CircuitVerse's hardware synthesis pipeline from a legacy server backend to a fully offline, zero-latency WebAssembly execution environment. By integrating the YoWASP engine within a dedicated Web Worker inside the Tauri desktop app, the project delivers client-side Verilog synthesis with a reactive Pinia state architecture, custom topological circuit layout, a full Vitest parity test suite, and contributor documentation, all without affecting existing web users.