Structured Format for Saved Circuit Data

CircuitVerse currently saves circuits based on visual layout rather than logical connections, resulting in unpredictable save files that prevent meaningful version control, complicate Verilog synthesis, and hinder data analysis. To solve this, this project introduces a deterministic, canonical JSON format. By utilising Kahn's algorithm to map dependencies, the new format ensures components are always saved and loaded in the correct sequence, regardless of where they are drawn on the screen. The key deliverables include a smarter export/import engine, an automated, zero-loss migration tool to smoothly upgrade all legacy .cv files to this new standard, a highly optimised single-pass Verilog generator, and an interactive developer UI featuring real-time JSON previews, copying, and downloading.