Hardware in the loop CI

GNU Radio’s current CI system relies on software-based testing, which cannot capture real-world SDR behavior and hardware-specific issues that arise under actual RF conditions. This limits the reliability of validating signal processing blocks before deployment. This project proposes a Hardware-in-the-Loop (HIL) Continuous Integration framework using CortexLab to extend GNU Radio’s CI pipeline with automated hardware validation. The system detects hardware-relevant changes in pull requests, maps modified blocks to predefined test configurations via a registry, and generates experiment artifacts (tx.py, rx.py, analyze.py, scenario.yaml) dynamically. To ensure efficient resource usage, the pipeline introduces a maintainer-controlled HIL execution step, allowing prioritization of critical PRs instead of fully automatic triggering. After reserving SDR nodes, a lightweight validation test is executed to verify hardware readiness before running full experiments. Each experiment is executed iteratively across multiple input configurations, and results are analyzed using block-specific metrics such as frequency error, amplitude deviation, SNR, BER, and stability. The system produces structured outputs that determine a final PASS/FAIL decision integrated into the CI workflow. Robust error handling mechanisms are included to manage failures in node allocation, execution, and result analysis.