Using AI to Improve Open-Source IP

Millions of lines of open-source Verilog exist but remain verbose and hard to maintain. TL-Verilog offers a cleaner abstraction, but almost none of this codebase has been converted. This project strengthens the LLM-driven conversion pipeline in the conversion-to-TLV repository by improving error recovery, refining prompt recipes for complex Verilog patterns (FSMs, parameterized modules, arithmetic pipelines), and applying the flow to real open-source modules including RISC-V components. All conversions are formally verified using SymbiYosys and EQY, generating high-quality training data for future LLM improvement. Deliverables include a fast working failure-classification system, improved prompts.json recipes, 10+ converted and verified modules, and structured training data registered in the project repository.