Free and Open Source Silicon Foundation
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GSoC Participation History
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PeakRDL Exporter Plugin for CSR Visualization on Makerchip
The project aims to add an exporter plugin for PeakRDL that enables a high level visualization for control & status register (CSR) design using...
Device-Under-Test Python Typing Stub Generator for cocotb tests
This project aims to create a tool that automatically generates Python typing stubs for the Device Under Test (DUT) in cocotb-based hardware...
OpenRISC Linux Feature Development
Jump Label Implementation aims to eliminate branch overhead in kernel code by dynamically patching JMP/NOP instructions at runtime using GCC's...
Architectural Improvements to OpenPiton+Ariane for RISC-V Profile Compliance
This project aims to enhance the OpenPiton+Ariane architecture to progress toward RISC-V RVA23 profile compliance. The primary focus will be...
Metro-MPI++
Modern RTL simulation is computationally expensive and often limited by single-node processing capabilities. This proposal aims to improve...
ZynqParrot RISC-V Tracer Implementation
This project seeks to enhance the ZynqParrot environment by integrating a RISC-V trace module that adheres to the official RISC-V trace...
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