Robust Implementation and Verification of the RISC-V Svadu Extension for Ariane+OpenPiton

This project aims to bring Ariane+OpenPiton closer to RISC-V RVA23 compliance by adding support for the Svadu extension. By enabling hardware-managed Accessed and Dirty bit updates, Svadu eliminates unnecessary software-managed page faults and improves virtual-memory efficiency. I will implement the required changes across the PTW, TLBs, LSU-side update path, and a new hardware unit, Page Table Entry Updating Engine (PUE), while building a robust verification framework based on Spike, Verilator, and handwritten assembly tests. In addition to a complete Svadu implementation, the project will deliver evaluation results, reusable verification infrastructure, and upstream-ready contributions for future RISC-V MMU-related RVA23/RVB23 extensions.