Micro Electronics Research Lab - UITU
Accelerating Engineering Innovation
GSoC Participation History
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Automated UVM Tuning Orchestrated Via AI Reasoning
Verification in hardware design is a time-consuming and complex task as well as requires manual effort to update UVM testbench components...
Integrating TCAM IP into Chipyard via MMIO and RoCC Interfaces
This project focuses on integrating a Ternary Content Addressable Memory (TCAM) module into the Chipyard SoC framework to enable high-speed parallel...
AEGIS - AI-Enhanced Generation of Intelligent Scenarios
AEGIS automates hardware verification by using AI to generate optimized test cases. Parses Specifications: Extracts key features (interfaces,...
Running Secure and Vectorized Applications on SoC-Now
This project aims to develop and benchmark high-performance applications that leverage the modular SoC-Now platform, which integrates RISC-V cores, a...
PyUVM-Based General Testbench for RISC-V Cores
As RISC-V adoption continues to grow, verifying functional correctness across various implementations becomes increasingly challenging due to the...
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